EC 462 Mixed Signal Circuit Design || Common Source Stage- Lecturer 1

Hi all, today we are starting our first module The topics in the first module are CMOS Amplifiers In CMOS Amplifiers, Common Suisse, Common Gate, Common Drain Configurations and Cascoded Stages These are the topics in the first module First, we will learn Common Suisse Stage What is Common Suisse Stage? We have studied in Electronics and Circuits What is Common Suisse Configuration? Common Suisse Configuration is The Suisse of the transistor is common to both Input and Output What is common to Input and Output? Suisse is common In the case of a MOSFET This is its Suisse This is its Drain This is its Gate You all know about MOSFET Terminals What is Suisse in this? Grounded Since Suisse is grounded Input is applied across Gate and Ground Gate and Suisse are across Output is applied across Drain and Ground Drain and Suisse are across That is why we call this configuration as Common Suisse Configuration We have studied the small signal model of Common Suisse Configuration We have studied in Circuits This is the small signal diagram of Common Suisse Configuration Input Terminal is kept open Because Input Resistance of the MOSFET is a very large value In the case of a MOSFET Since Input Resistance is a large value Input Terminal is kept open There is a Current Suisse in Output There is a resistor called RD I have written Current Suisse as gm into V1 Current Suisse is this RD Resistor It is kept open in Output Output is this Drain This Drain and this Suisse This is Suisse Suisse is grounded This Suisse is also applied across Output is applied across For small signal M1 converts the input signal variation to Proportional Drain Current changes and RD transforms the Drain Current to Output Voltage Common Suisse is working for a small signal In the case of a small signal M1 converts the input signal variation Transistor converts the input signal variation to Proportional Drain Current RD is given here RD is the resistor RD converts the Drain Current to Equivalent Output Voltage RD transforms the Drain Current to Output Voltage Channel Length Modulation Channel Length Effects In the case of MOSFET Channel Length Modulation If we neglect Channel Length Modulation From the small signal model We can write like this Vin is equal to V1 And Vout is equal to Vout is taken from here Vout is equal to gm into Current into Resistance gm into RD gm into V1 into RD Or gm into V1 into Current into RD The direction of the current is here Since the direction of the current is here What do we give here? We give a minus sign These are the same things we have learned in the circuits Input is Input Voltage Vin is equal to V1 Vout is equal to gm into V1 Current into gm into V1 into Resistance RD gm into V1 The direction of the current is not here Instead, the direction of the current is here Isn't it? So, we have to give a minus sign here From here Vout divided by V1 is equal to V1 is the same as Vin Vout divided by V1 is equal to We can write it as minus gm into RD We can say that Voltage gain of the common switch stage is limited by the supply voltage gm is a term that we have learned gm is a transconductance gm's equation is gm is equal to root of 2 mu n Cox into W by L into Id gm's equation is root of 2 mu n Cox into W by L into Id This value mu n is mobility Cox is Oxide Capacitance Oxide layer length There is a capacitance effect That is Cox W by L is Mosfet's width to length ratio In this, we take the value of gm and substitute it in this equation Av is equal to minus root of 2 mu n Cox into W by L into Id into RD We can conclude like this If Id or RD is increased If Id or RD is increased The voltage drop across RD is equal to Id RD Ok Voltage drop across RD is equivalent to Id RD We can change the gain by increasing Id or RD We can change the gain We have learned This transistor If this transistor is in saturation If it is in saturation Vdd minus Id RD is greater than Vgs minus Vth Vdd minus Id RD is greater than Vgs minus Vth If we rearrange this Id is equal to Id RD is less than Vdd minus Vgs minus Vth Id RD is less than Vdd minus Vgs minus Vth That is the reason to operate this transistor in saturation region That is the reason We have learned so many things We have drawn the common source configuration We have drawn the small signal model In small signal model, the input is Vin We have not drawn the input resistance or internal resistance because in mosfet case, internal resistance is a big value That is why we have shown it Now, the current source is gm into small signal model It is a general small signal model gm into V1 On the output side, we have drawn this resistor This is the small signal model Now, we can write Vout is equal to minus gm V1 into RD What is the reason to take minus sign? The reason to take minus sign is the direction of current is not this direction but this direction The current is going this way That is why we have taken minus sign We have written minus gm into V1 into RD We have written Vout divided by Vin is equal to minus gm into RD What is gm? It is a transconductance The equation of gm is root of 2 mu n Co x into W by L into I d You have to learn it If you want to do problem, you have to learn it Now, Vout by Vin is equal to minus gm into RD Now, we substitute this value for gm Now, What is the condition to work in saturation? Vdd minus I drd is greater than Vgs minus Vth or I drd is less than Vdd minus Vgs minus Vth Vdd minus of Vgs minus Vth