Lecture 13 Module 2

Now, welcome back. So, let us take, let us use the framework that we just talked about and see how we can use it in our commonsense amplifier. Mind you, this is again a repetition of what we have done in the previous lecture. But in this lecture, the aim is to, the aim is to formalize the treatment of using the quiescent condition and the incremental condition separately and combining them. So, because this is important because we will be using this framework for the rest of the course, ok. So, this is the standard commonsense amplifier topology that we, that we started off with even before we knew that this was a commonsense amplifier. So, what should we do? First step is to find out the Q points. So, this is, let me mark this as Q point analysis. So, what should we do? We should get rid of the incremental, any incremental stuff. So, this is what we are left with, right. From there, from here what will we find? We will find Vgs, we will find Vds, we will find Ids, right. So, then what is the second step? The second step is do small signal analysis or incremental analysis. So, what will you do? You will essentially replace, you will essentially replace all the non-linear elements with a, with a incremental equivalent, right. So, the incremental equivalent of our, for MOSFET is the incremental equivalent of the 2 port network, right. So, and, and we know that given the current voltage equations of the MOSFET in saturation, we know that the incremental equivalent is this. We get rid of all the constant sources and how should we get rid of the constant sources? Since we have a Vdd, since we have voltage source, we can short it. If we had a current source, we should have had to, we would have had to open it, right. So, this is Rs. So, this is gm times this voltage Vg minus Vs or Vgs, ok, ok. So, if we do this analysis, what, what do we get? We get this voltage to be equal to Vi, correct. So, if, which means Vgs is equal to Vi, which means this current becomes gm times Vgs. This current is the same as this current, which means this voltage here is what? What is the drop across RL? The drop across RL is gm times Vgs, but in which direction? In this direction. Since the bottom side is, bottom side of RL is grounded, so this voltage will be minus gm times Vgs times RL or in other words, which is equal to minus gm times Vi times RL, right. So, what is the total, what is the, what is, so what is the total Vgs? So, when you have to find out total, so we have to add up, now in order to find out, so we have to find, let me not go into a different page, that will make it complicated. So, let me do this, total InV. So, what you have to do? You have to find out, you have to get the Vgs, Ids, Vds, you have to find out Vgs, Ids, Vds and you total them, right. So, you find out, you total them as in Vgs becomes Vgs plus small vgs, Ids becomes Vds plus small ids. Similarly, Vds becomes Vds plus small vgs. Let me ensure that we have used the same terminologies, yes, right. So, 2 step, 3 step process, first step, you find out only quiescent, second step, you linearize the network, find out its incremental equivalent and solve it to find out incremental, third step, add them together, you get the total current and voltages. And why is total essential? Total is essential because you need to ensure that the circuit, the transistor still operates in saturation even when there is a signal swing. It is not sufficient to only ensure that the transistor remains in saturation only under quiescent condition. The transistor needs to be under appropriate biasing regime even in the presence of signal swing and how will you ensure that? In order to ensure that, you have to find out the total currents and voltages, correct, ok, great. So, now let us take the example of this common source amplifier and see where that leads us. So, what did we see? We saw that now, let me just, I will assume that we know what the common source amplifier currents and voltages are, right. So, what should we see? We should find out what is the maximum swing if I have to find out, right and I mean to find out the maximum or minimum Vi for which M1 always remains sufficiently into saturation, remains in saturation. What should we do? Firstly, we need to establish what are the total currents and voltages. So, what is the total? The total, so total current, total, I mean let us do the saturation first, saturation condition first. So, Vd which is equal to Vds, right, Vds which had been found from quiescent conditions plus Vds. What is Vds? Vds is, small vds is, again small vds is minus gm times Vi times RL, right. So, this is the small vds or incremental vds. So, this becomes Vds minus gm times RL times Vi, ok. So, this is Vds, ok. Similarly, what is small v, small v or total Vgs? Total Vgs is Vg plus Vds which is equal to Vgsq, the one that we have applied plus Vi, right, ok. So, let me use q here, otherwise it will not be consistent, ok. So, now what is the condition for saturation? The condition, condition for saturation is Vd should be greater than equal to Vg minus threshold voltage, right. So, since this is the case, I need not even bother about source, but in our, in this example, the source is grounded. So, it does not really matter whether I am expressing in terms of Vds, Vgs or only Vd or Vg, which essentially, this essentially gives us the condition that Vdsq minus gm times RL times Vi should be greater than Vgsq plus Vi minus threshold voltage, right, which means 1 plus gm RL times Vi should be less than equal to Vgsq minus threshold voltage, which is a DC overdrive, right, minus Vgsq, which essentially boils down to Vi should be less than Vgsq minus threshold voltage minus Vdsq by 1 plus, and if Vi is Vp sin omega naught t, right, if Vi is less than sin, sin of, Vp sin omega naught t, what does this, what does that condition impose? The condition essentially is telling us that in order to always ensure the transistor is always in saturation, even when I have applied a sinusoidal input, your Vp max should be less than, this is V overdrive minus Vdsq by 1 plus gm RL. Let me say V overdrive quiescent q, because we are dealing with quiescent conditions, ok. So, this is to ensure saturation. So, this is when the signal, when Vi is here, right. So, this is the max we are talking about. We are not talking about the bottom cycle, right, we are not talking about the negative cycle, we are only talking about the positive cycle, because the transistor can go out of saturation, only the positive cycle of, in case of a common source amplifier, ok. So, now naturally what happens, if in the negative cycle, naturally, I mean, we have talked about this. So, in the negative cycle, going out of saturation is not, no longer a problem because the gate voltage is going down, drain voltage is going up. So, the transistor is comfortable in saturation, but what is the problem? The problem is my current is decreasing, right. So, what is the problem? So, what is the other condition? The other condition is, what is my total current? Total current is equal to Ids is Idsq plus small ids. So, Idsq we have found out from our quiescent conditions, so mu n C ox W over 2 L Vgs minus Vg whole square, right. So, we have found out Idsq. What about small ids? What about incremental Ids? What is the incremental Ids? Incremental Ids is gm times Vgs, right. So, incremental Ids is gm times Vgs and Vgs is equal to Vi in this case. So, this becomes plus gm times Vi, right. So, what do you want this to be? What is the inequality that we are bothered about in this case? So, let me, let me sketch inequality that we are bothered about in this case. Let us say this is Idsq, this is with respect to time, ok. So, let me sketch it in the next page, ok. And let us say this is Vi, this is Vi, ok. So, what is going to happen? So, let us say this is Idsq, if this is and that and the Vi is also sinusoidal, what is that sinusoidal voltage lead to? So, it will lead to also a proportional current which is gm times Vi. So, and you have to essentially add those two up and you will get, you will get a corresponding sinusoidal current on top of Y set, right. So, this will be gm times Vgs or gm times Vi in this case. Similarly, this will be gm times Vgs, the magnitude of that will be gm times Vgs or gm times Vi. Now, what do you think? Do you see a problematic situation arising, right? You must be, I mean, just look at this margin that I have when the, when the current is going towards the negative cycle. What is that margin that you are have? The margin that you started off with was Idsq, but the margin is shrinking as, as the current is lowering, right? As the, in the negative half cycle of Vi, that margin is shrinking and how much can that margin shrink? The margin can shrink to the level of Idsq, right? So, the max, which essentially means that if you keep on increasing Vgs, you run into the trouble of shutting the transistor, right? So, what is the problem? The problem is, if you increase, if Vgs increases, total Ids decreases, right? If Vgs increases, total Ids decreases and how much total Ids can decrease? It can at max go to, go to 0, right? Or rather at min it can go to, go to 0, which means what is the other condition? What is the limiting condition on the negative side for Vi? So, the other condition is Ids, so limiting condition then becomes, so limiting condition for Ids greater than equal to 0 becomes Idsq, let me just say the limiting condition for keeping the transistor on is to ensure total Ids is greater than, right? So, in this case, so Ids, if I say this has to be greater than equal to 0, what does this mean? This means Idsq plus gm times Vgs should be greater than equal to 0, right? So, this becomes gm Vgs should be greater than equal to minus Idsq, right? Yes, which means Vgs should be greater than equal to minus Idsq over gm, right? Which now note that in our case, which value, what is Vgs? Vgs is going, Vgs is a sinusoid which is going up in one cycle and one half cycle and going down in another half cycle and for cutoff condition, only when the, when the negative peak appears, right? When basically when Vgs is equal to minus Vp, we will end up with the issue with cutoff condition, right? So, which means that when Vgs is minus Vp, this should be greater than minus Idsq over gm, since cutoff condition is governed, is decided by negative half cycle, right? Which essentially means that Vp should be less than equal to Idsq over, right? If this height, let me sketch it in a different page. So, this is the input voltage Vi, say this is the total current. So, this is Idsq, the current, total current becomes, the total current becomes actually 0, it touches 0, total current touches 0 when this input sinusoid or let me just say Vgs in this case, this Vgs becomes Idsq over gm, right? So, note that this everything came from quiescent plus incremental analysis. So, we found out what is the quiescent drain current and we found out what will, what will be the change in the drain current in the presence of a swinging Vgs and we notice that if Vgs goes down, the total drain current will also go down and how far it can go down, it can go down to at max 0. So, this is becomes a limiting condition of the transistor current going to 0 under the, when we have done the analysis using the framework that we have developed, right? So, now essentially you would have seen that the, we have gotten two constraints. So, so we get to summarize, so we get two constraints on Vgs or Vi in this case, for the, to keep M1 in saturation and away from, those two constraints came from two different conditions. One is to keep the transistor away from saturation and other is to keep the transistor away from cut-off. So, after you do this, so what, so what is the, what are these constraints? The constraint was Vgs or in this, the constraint that we got was Vi should be less than V over drive Q minus threshold voltage by 1 plus gm RL and another constraint was Vi should be less than equal to IdsQ over, right? So, this is the saturation constraint, this is the cut-off constraint, right? And these two and the values that you will get by analyzing these two constraints will not be same, need not necessarily be the same. So, so which value will you choose? Let us say after doing, after doing the saturation constraint, I got 100 millivolt, right? I got the constraint of Vi should be less than 100 millivolt and after doing the cut-off constraint, I got Vi should be less than 50 millivolt. Which one should you choose? Obviously, you should choose that one for which both the constraints are net, which means we will choose Vi to be less than equal to 50 millivolt. Because if you choose Vi to be less than 50 millivolt, you not only satisfy the cut-off constraint, but also satisfy the saturation region constraint, right? Okay, so we will, we will stop here for this lecture. And I request you to pay particular attention to this lecture because this will form the backbone of many of the analysis that we will be doing for almost all the architectures that will be, that will fall, right? Okay.