Lecture 14 Module 01

Welcome back, this is lecture 14. So, in the previous lecture, we saw some constraints on the common source amplifier with respect to, with respect to the amount of signal that you can, that you can hope to apply at its input while keeping the transistor in proper operating region, that is, it should be in saturation and obviously, away from cutoff across the entire range of the signals, right. So, while, while we were finishing of the lecture, we arrived at two constraints, one was obviously, when the signal was going high, right, one was, if you recall, so what we saw was, if the signal swings, the sinusoidal, the signal, incremental signal is sinusoidal, this signal will swing between the gate and the source on top of a quiescent VGSQ and while it does so, the drain voltage swings in a anti-symmetric manner, right and if there is a gain, the drain voltage will swing, amplitude of the swing of the drain voltage will be higher than the amplitude of the swing at the, at the gate, right. Now, what happens, what happens when the input, when the gate voltage increases and the drain voltage decreases, what happens? The transistor is going towards, towards linear region, right. So, you will have to be careful while choosing, choosing the input swing or in other words, if you are designing a transistor, you will have to choose the quiescent drain voltage in such a way that for the entire range of signal swing, the transistor remains in saturation, right. This is as far as, as far as the condition of signal swinging high is concerned at the gate. Now, what is happening when the signal is going low? When the signal is going low at the gate, at the drain it is going high, right. So, saturation is no longer a problem but what is the problem? The problem is the transistor, the current in the transistor is decreasing, right and we said that while the current was going low, the condition that we imposed was total I d s was the quiescent I d s, that is I d s q plus g m times V i, this is the total current and this we have to ensure that this never goes to 0. If this goes to 0, then there we are, then we are in trouble. Now, what is happening or rather in this case V g s, right, if you have to make it genetic, it should be V g s. As it turns out in case of a common source amplifier or in the configuration that we are looking at, V g s happens to be equal to V i, but you have to be careful, you do not, you should not write g m times V i all the time, it is, mind you, it is always g m times V g s. If V g s is equal to V i, well and good, but it need not necessarily be the case all the time, right, ok. So, I d s is equal to I d s q plus g m times V g s and we have to ensure that this always remains greater than 0. And what happens at the negative cycle? At the negative cycle, if this is a sinusoid, on the positive cycle it goes to the input V g s goes to plus V p, right. If the sinusoid, if this sinusoid is V p sin omega naught t, on the positive half cycle this goes to, the input goes to plus V p and the negative half cycle the input goes to minus V p, right. So, what is the constraint that will limit our condition that the transistor should, is away from cut off? The condition that will limit us will be I d s q plus g m times minus V p will be greater than 0, which means V p should be less than I d s q over, right. So, this was the condition that we derived as we were finishing off the previous lecture. Now, some of you might have the question that this probably does not seem right because my current voltage equation for this transistor, right, the current voltage equation for this transistor is I d s is mu n C ox W by 2 L V g s minus threshold voltage whole square, right. And on top of that if I apply a sinusoid, right, what does V g s q lead to or what does V g s leads to? So, now I knew V g s is, V g s is V g s q plus V p sin omega naught t, right. And what will happen when I am in the negative half cycle or in other words when I am at peak negative cycle, V g s will be V g s q minus V p, right. So, which means at sin omega naught t is equal to minus 1, what is going to happen? I d s will be half mu n C ox W by L V g s q minus V p minus threshold voltage whole square. And in order to ensure that the transistor is away from cut off, all we have to ensure is that this remains greater than 0, which means what? Which means we have to ensure that V p is less than equal to V g s q minus threshold voltage, right. Or in other words we have to ensure that V p is less than V overdrive by center, right. So, this condition and this condition, right, this condition and this condition are the same. So, let us see. So, the condition that we got from, so this is constrained from large signal analysis. So, why do I say large signal? Because I have not taken any small signal approximation, I took the total current voltage equation and I simply figured out when the current to 0, right. However, the condition that we got, however, the condition that we got here is from, in, is from quiescent plus small signal analysis, right, quiescent plus small signal incremental. So, in other words the condition that we got was V p is less than I d s q over g m, this is constrained from small signal analysis. Now, are they same? Let us see. So, if I replace, if I replace this I d s q and g m with that expanded version, so what do I get? So, V p should be less than half mu n C ox W over L V g s q minus threshold voltage whole squared divided by g m, g m is again mu n C ox W over L V g s q and threshold voltage, right, which means that V p should be less than half V g s q minus threshold voltage, correct. So, so this full blown analysis, the large signal analysis was giving me this constraint and the small signal analysis is giving me this constraint. Note that they are off by a factor of 2, right. Now, the question might, that we might ask is that why are they different, right? There are two questions to be asked, like why are they different? Are you comfortable with the fact that they are different? And the second question is that if we are comfortable what is this factor of half? What does, what is the implication of this factor of half? Now, coming back to the first question, why are they different? We should not be surprised here because, because what is small signal analysis? In a small signal analysis, we do not consider the entire current voltage equation, right? We only consider the linear term while saying that the higher order terms even though they exist, we will neglect them because it is difficult to deal with higher order terms. So, we have purposefully, we purposefully omit some, some accuracy, right? We give away some accuracy in search of, in search of mathematical ease, right? So, which essentially means that when you do a small signal analysis and you do a corresponding large signal analysis, you are bound to get a different result, ok. So, that is as far as why are we getting a different result, the answer to that question is concerned. However, now the question is what is this half, what is this half doing here and should we be bothered about this or should we be ok with this limit that we got from the small signal analysis of V p or should we stick to, should we stick to the one that we are getting from large signal, signal analysis, right? So, let us, let us spend few minutes investigating that, ok. So, let us say, let me just sketch one transistor without sketching the whole, whole biasing network and everything. Let me just say that this is V gs, V gs and the current through this is I ds. What is this I ds, V gs characteristics? What does it look like? Note that this I ds, V gs characteristics is nothing but the plot of the equation half U n C ox W over L V gs minus threshold voltage whole squared, right? So, what does this look like? This looks like, I mean if we assume that I ds is equal to 0 for a threshold voltage less than 0. So, till, sorry I ds equal to 0 for voltages lesser than threshold voltage. So, till threshold voltage I do not have any current, above threshold voltage I should see a, I should see a parabola, right, ok? Let me draw a cleaner parabola if I can, ok. And let us say threshold voltage is equal to 1 volt, right? And let us say I am, I am trying to figure out, I have biased my circuit in such a way that V gs is equal to 2 volt, right? So, let us mark off a value of 2 volt here. So, what is that I ds Q? The I ds Q will be that value which corresponds to V gs of 2 volt, right? So, I will have some I ds Q which corresponds to V gs of 2 volt, ok. So, what does, now if I say that using small signal incremental analysis, small signal plus quiescent incremental analysis, I got I ds that is a total I ds which is equal to I ds Q plus gm times V gs. What am I saying? What is gm? What is gm? What is the definition of gm? gm is nothing but the slope of, slope of I d V gs characteristics, I ds V gs characteristics at the operating point V gs Q equal to 2 volt, right? So, if I, if I, if I sketch a slope, right, so this slope is, is, is a gm, right? So, this is the slope, right? So, this is the y axis, correct? So, I can say that this is, if you recall the equation of a straight line, so this seems ideally similar to the equation of a straight line, right? So, what is the equation of a straight line in a xy plot? If I, if I jog your memory, y is equal to mx plus c is the equation of a straight line. What is corresponding to y here? I ds corresponds to y. What is corresponds, what corresponds to x? What corresponds to x in this case? Your V gs, right? Your V gs corresponds to x. So, this is what is called corresponds to m, gm corresponds to m and what corresponds to c? I ds Q corresponds to c. So, this become I ds Q. Note that this is constant, right, ok? However, there is a, there is a slight difference. The slight difference is that here we are bothered with, we are taking into account the total V gs, but in this equation, we are only taking into account the incremental V gs, which means that the plot would have shifted along the x axis, but that is a matter of, that is a matter of detail, right? So, that should not bother us too much here. Now, the question that we are asking, the question that we are asking is that when we set I ds to be is equal to 0, right? When we are setting this I ds to be equal to 0, what are we essentially doing? We are essentially extrapolating this plot, we are extrapolating this plot and seeing where it touches, where it touches 0. So, I think I did not sketch the plot properly. So, if I extrapolate this plot, so it will, it will touch the, it will touch the y axis, x axis somewhere. So, the value of V gs, right, the value of V gs, what is V gs? I am sorry, I mean, I am making a mess out of this plot. Let me try to be a bit more clear. So, this is the, this is the, this is the equation on the straight line. When we say that, when we say that our, our signal swings in a sinusoidal fashion, what are we essentially saying? We are saying that my V gs, V gs is equal to V p sin omega naught t and V gs is swinging on top of what? V gs is swinging on top of the quiescent point and what is the quiescent point? The quiescent point is V gs cube, right? So, if I say that, if I, if I say this is the time axis, right? So, this is V gs. So, when I have, when the signal is sinusoidal, what is happening? Essentially what is happening is the signal is swinging like this, right? And when the signal swings like this on, on the voltage domain, what is happening in the current domain? In the current domain, the current is swinging between this point and this point, right? So, the current is swinging between this point and this point, right? So, this will be your, this will be your I ds cube, sorry, this will be your delta I ds, correct? So, this will be your small I ds, ok? So, when we say that, that the total I ds goes to 0, what are we essentially saying? We are saying that we are trying to figure out this point, we are trying to figure out this point where, where, where the straight line meets the x axis or the voltage axis, ok? And what is this value of V gs? In, in, in this, in this plot, what is this value of V gs? The value of V gs is nothing but the deviation from, let me use a different color, the value of V gs is nothing but the deviation from the quiescent point, right? At which V gs max, this is not visible, this is, this is V gs max for which I ds goes to 0, ok? So, this becomes, so this essentially becomes your, this becomes the, the pictorial definition of where I ds goes to 0 using the small signal plus quiescent, quiescent plus small signal picture. However, if you stick to the, if you stick to the large signal picture, large signal picture, what is, what is it that you will get? You will get that, you will get this to be your V gs, right? So, using large signal picture, this is the V gs max for I ds equal to 0 using large signal picture, correct? Now, clearly in the pictorial definition, you see that there is a difference between the small signal and the large signal picture simply because I have a parabola. It is basically the current, the current voltage relationship of a MOSFET is that of a parabola and the fact that that half, the factor of half comes into picture is basically the property of the slope of, of a parabola, right? Now, note that if I, if you, if you again go back to the previous lecture, what we established, the stuff that we established was in order to ensure our small signal models are valid, we have to ensure a certain condition, right? What was the condition? The condition was, the condition was that the incremental V gs has to be much, much less than the overdrive, right? The incremental V gs should be much, much less than V gs q minus threshold voltage. Now, if you allow the signal to swing as high as the overdrive voltage, right? So, if you allow the signal to swing as high as the overdrive voltage, you are definitely not honouring the, the constraint on small signal and if you do not honour the constraint of small signal, what is going to happen? Your circuit will become terribly non-linear, right? You will have higher order terms, you will have, if you, if you, if you input a sign, input, if your input is E p sin omega t, you will, you are going to get output at omega naught and also, but you are also, you will also be getting outputs at 2 omega naught, because you have the square terms that will come into picture and why will they, they start dominating? They will start dominating because your signal is swinging so much that your, your small signal validity approximation is no longer, no longer valid, right? So, so given that constraint that we have to stay away from the signal swing of as high as the threshold, as high as the overdrive voltage, right? So, we cannot ever apply a signal which is equivalent to, we cannot ever apply a signal between the gate and the source of a transistor which is equivalent to its overdrive voltage, right? Which means we have to apply a lower signal and, and a lower value of the signal and, and the, and, and the constraint on, and the analysis of incremental plus, plus small signal is enabling us, right? The, the, the result that we are getting by using incremental plus, the result that we are getting by enabling the quiescent plus small signal approximations is giving us the, is giving us the, a better perspective of, of how to handle, how to handle small signal models and the results that we are getting out of the small signal by, by setting this total current to 0 also, also honours the small signal approximation, right? So, so going forward, hence going forward, we will be using this constraint, right? We will be using this constraint of, for setting the current to find out the maximum current or the maximum swing that we can have, right, at the input in order to, in order to keep the transistor away from cutoff, we will be using this constraint that is the quiescent plus incremental and we will not be using, we will not be using the large signal constraint of setting the Ids to be equal to 0, right? So, this is again a very important, a very important outcome of this, of this discussion. So, we will be, we will be having a few assignments on small signal model, on, on swing limits, what is the maximum swing that you can apply from an input while keeping, while keeping the transistor in saturation and away from cutoff. So, I hope you will be, you will be able to hone your skills and become comfortable with dealing with this, this quiescent plus small signal models, right?