Lecture 15 Module 02

Okay, so what is the conclusion of whatever we discussed, so quickly recap. So if you have a structure like this and we want the capacitor to act as a short circuit at the frequency of interest, right and so what will be the voltage at this node, what will be the total voltage Vg, the total voltage Vg will be and I can use superposition because completely linear network, what will be the superposition of this V, we have two sources, one is Vdd, one is Vi, right. So if I assume in case of superposition, I take one source at a time and de-energize the other source, both are voltage sources, de-energizing a voltage source is essentially equivalent to, is essentially equivalent to shorting it, let me connect everything together so that it makes a bit more sense, right. So if I assume that Vi is shorted, what will Vg be, Vg will be Vdd times R2 by R1 plus R2 and if I subsequently assume Vdd is shorted, what will Vg be, this will be, if I further assume that the C is large enough to be treated as short circuit, so this will be approximately equal to Vi times R1 parallel R2 by Rs plus R1 parallel R2, right, this is assuming C is large now, right. So what is the assumption, what is the total voltage across the capacitor, what will be the total voltage that we will see across the capacitor, now let me mark the voltage in this direction, let us say Vc, so what will be the total voltage across the capacitor, Vc will be, again I can do superposition, right, so what will be, if I assume Vi to be de-energized, Vc will be what, Vc will be simply Vdd times R2 by R1 plus R2 and this is, this is expected because that was the quiescent voltage that we, that we anyways wanted. Now, in the, now what is the effect of Vi, again because I am using superposition, I can short Vdd, if I short Vdd, R1 and R2 come parallel to each other, what will be the, what will be the voltage then, voltage across capacitor will be nothing but whatever we saw in the earlier example, it will be Thevenin by, right, V Thevenin by 1 plus j omega Rth times C, ok and V Thevenin in our case was Vi, right, V Thevenin for the capacitor was Vi and if this omega naught, if C is much much greater than 1 by omega naught Rth, right, your Vc will be R2 by R1 plus R2. So as you see, if the, if you, if we follow the rules, right, if we, if we follow the sizing rules of the capacitor, what we will see is that the capacitor is only holding, is only holding the DC portion of the information, right. So this is the DC portion of the information and this is the, this is the AC portion of the information. So this is amplitude or rather this is the response, voltage response across capacitor, right, voltage response across the capacitor at steady state. When I say steady state, what I mean is that you have, your Vi is a sinusoid, you have applied the sinusoid and you have waited for infinite time, no transients we are talking of, there is no transient effects that we are talking about here. So the voltage across the capacitor is Vi by 1 plus or rather the voltage response of the capacitor is Vi by 1 plus j omega naught Rth C and this, the other one, this one is essentially the bias at, that bias voltage of the capacitor is holding, right, DC bias or DC voltage, we simply say DC voltage. So as you see the capacitor is doing, doing two jobs here, one is it is holding the DC voltage across it and also it is, it is allowing the, it is allowing the AC voltage to go through, ok, ok, great. So now, now that we have the biasing picture at the, at the, at the input side, let us, let us redraw our common source amplifier, right, so what is our common source amplifier now? Let us go to a new page, the common source amplifier now, at least at the input side is, looks to be sorted, right, so this is VDD, ok and this is RL. So is, I mean seems like if I size C R1 and R2 accordingly, right, it looks like, I mean all our problems are solved, we should be, and if we take the output, if we take the output from this node, it looks like we are good to go, right, but the question is are we? So, it turns out that is a slight bit of complication, the complication is again a practical one, remember I told you that there is a problem that you cannot have access to both terminals of a source, right, similarly you need not necessarily have access to both terminals of a load because what is this RL, what is this RL? This RL might not be, might not be a actual resistor, this RL might be the input impedance of another stage that it is driving, so which essentially means that you only have access to one terminal of the load and not the other terminal that you will just connect it to VDD, right. So, essentially the problem is we seldom have access to both terminals of RL, okay, so which means that your RL is just like your source, your RL, one terminal you can assume it to be implicitly grounded, right and you have access to this terminal, which means you cannot put RL between, between the VDD and the drain of the transistor, okay. So, now what should we do? Input side we did something to figure, but what should we do with the output side? Note that the first condition, what is the first condition? The first condition is that we need to ensure that the transistor is in saturation, right, without that we do not have any story to tell, right. Without that you cannot make the amplifier work like a, you cannot make the transistor work like an amplifier simply because, I mean go back to the small signal model of an amplifier, the GDS or the Y22 or the GDS has to be equal to 0, if the transistor is not in saturation that is not possible, hence it is a big problem, right. So, what is a, again if we go back to our drawing boards, what is a easiest way of ensuring the transistor is in saturation? One is to say that I will directly connect the drain to, drain to the VDD, okay, right. So, then what should we do with RL, how should I connect, how should I connect RL because ultimately, what is the, what is the incremental equivalent of this, what is the incremental current? The, what will be the total current of the transistor, total current will be Id plus an incremental current, right, some del I or let me say small id. The small id will be gm times Vg, right, gm times Vgs where s is grounded, so it is basically gm times Vg and if you have done a good job in biasing the input side, Vg will be approximately equal to Vi, then essentially the incremental current is still Id plus, capital Id plus small id or let me say idq plus small id. But where will this Id flow, where will this incremental current flow? This incremental current clearly will flow into the, into the VDD, right because incrementally this VDD is, is a short circuit, right, so this Id will, I mark Id with the magenta color, so this clearly, this Id will flow, flow into the VDD and whatever you do with RL, you will not be able to generate any voltage across RL, right. So, earlier how do we solve this problem? We put the RL in the path of Id, we put the RL between the drain and the VDD, so Id had no other option but to flow through RL, since Id was flowing through RL, it was generating a voltage proportional to Id and we were, we were reading that voltage out. But now as I said, since we do not have access to both terminals of RL, we cannot put RL in the, in the path of, in the path of Id. So what is the solution? Okay, so if this cannot be done, this cannot be done, firstly, I mean firstly, first things first, we cannot expect to get anything out of this, if drain is connected to VDD, right. If drain is connected to VDD, all the incremental current Id, right, this magenta Id will always go to VDD. So we have to, first things first, we have to prevent that, so how do we prevent that? How were we preventing it earlier? From drain being shorted to VDD, we prevented that earlier by, by connecting a resistor. In that case, it was RL, but in this case, let me say it is not RL, let me call this RD. I mean nothing innovative, D stands for drain, I am connecting it between drain and VDD, so I am calling it, calling it RD, okay, okay. So now, now this drain, what will be the, what will be the drain voltage? I mean this is nothing but the common source amplifier with, with RD instead of RL. So what will be the drain voltage here, what will be the total drain voltage here? This will be VDD minus Idq plus Id times RL, correct, okay, but ultimately what do I want? I want, I want the Id to flow into, flow into RL, right. I want Id to flow into RL because ultimately I want the voltage to develop across RL, right. So, so what, how do you think, can you, can you suggest a way so that if not full Id, part of the Id flows into RL, well one way to say is that I can, one possible way is simply to connect the drain of the transistor to RL, right. Then one might be tempted to say that this part of this Id, part of this Id will flow into RL and part of this Id will flow into RD, right. So if not, I mean earlier we are not getting anything, now we are getting something, this might be a, this might be a decent solution, right. But even before jumping into that conclusion, let me, let me, let me now point you, point out a important problem with this, with this type of, if you simply connect RL to, if you simply connect RL to the drain, right. So, what is the problem? Let us, let us start again from the beginning, let us assume the RL was not connected. What was the, what is the, what is the voltage, so what is the voltage at the drain? What is the voltage at the drain is VDD minus this, right. So let us, let us forget about, let us forget about the incremental Id, right. So the voltage, quiescent voltage, let me call this VD, so VDQ was VDD minus IdQ times, this is not RL, this is RD, I am sorry, RD, ok. So what is the voltage across RL, let me call it VRL. What is VRL? VRLQ is equal to 0, right, if VRL is equal, now what will happen if I connect these two, what will happen if I connect these two nodes, if I connect VD and VRL, forget about the incremental, forget about the incremental current, what about the DC current, what will happen to the DC current? So clearly some part of the DC current, some part of the DC current that was coming out of, coming through this will now flow into, flow into RL, right. What is the problem? The problem is then the value of VD will drop, the drain voltage will drop because now, now you are essentially loading the drain, you are essentially loading the drain voltage with, loading the drain with, with RL, in the, in the biasing picture also, right. So again, why are you loading? Because the moment you are connecting RL to VD, you are drawing current out of that node, right. So what is the crux of loading? If you are drawing current out of a load, of a node, after you have connected a load, the load, the resistance is loading the, loading the network. So here you are using RL, you are, you are loading, loading your common source amplifier, right. And what will happen if you load? It will draw some current out, whatever biasing you had envisaged earlier, right, after carefully writing out the equations, we will go for a toss, the transistor will, might not remain in saturation if you are not careful, right. So what is the, what is the problem? The problem is RL is loading, loading M1, right, RL is loading M1, therefore DC queue points will change. It is loading in the DC picture as well, right, ok. So let us, let us draw this, let us redraw. So let us see what is the problem. So let us forget about id for the time, small id for the time being. The problem is this is loading, right. So what, what is the solution? So let us say I knew a priori, let us say I knew a priori the voltage at Vd is Vdq. So let us say I knew this voltage is Vdq and somehow after I figured whatever Vdq was, right, I put a battery, let me do this. So let us say I knew this voltage is Vdq, Vdq equal to id, I mean Vdd minus id Rd, right and I, somehow I figured out what the battery, what the value was and I put a battery Vdq between, I mean in series with RL, right. So what is the voltage here now? The voltage here now is Vdq, right. So now if I connect these two nodes, what is going to happen? Do you think any current will flow through that blue line, through that blue wire? No, right, because both sides of the wire were at identical potential to start off, right. So there is no need, current only flows from higher potential to lower potential in order to equalize the, in an attempt to equalize the difference in voltages. Since there is no difference in voltage, no current, no DC current will flow, right. Since no DC current will flow, my, the quiescent point of the M1 will not get, will not get hampered, right, okay, great. So let me, let me make it a slightly better drawing. So what is the solution that we come up with? So the solution that we come up with is put a, identify whatever voltage Vd was, Vdq and put that, put that value, put, put that, put, include a battery of exactly that value Vdq. Now some of you might get angry with me and say that half the lecture you have told us that I mean I cannot use a floating battery, then how come I am using a floating battery suddenly. You are absolutely right, we cannot use a floating battery, but now we have a replacement. What is the replacement? An infinite capacitor, right. So instead of using Vdq, what will we use, we will use a, we will use a capacitor, right. So we will use a capacitor, let me call this C2 and let us assume C2 tends to, right. So if I use C2 and I use C2 tends to infinity, right. So, what will be the voltage, what will be the voltage across C2, what will be the voltage across C2 under DC condition, right. So voltage Vc2q, let us say Vc2q, the q stands for quiescent, what will be Vc2q? So clearly at DC capacitor is open circuited, no current will flow. So what is this voltage? That voltage is 0. What is Vd? Vd is Vdq, right. So Vc2q is Vdq, which is Vdd minus Idq RL, right. So, so the, so, so note that by putting a capacitor, we are not disturbing the, we are not disturbing the quiescent point of the, of the transistor, right. If we can, we can, if we can ensure that we are not disturbing the quiescent point of the transistor, that is a good start, right. The RL is no longer, RL is no longer loading the quiescent point of your, a quiescent operation of your transistor, ok, great. So what about, what about the AC condition, right? So let us, let us sketch the AC equivalent, right, before we go into the AC condition. Let us sketch the AC equivalent. Let us assume the gate is at Vg. What is the, what is the equivalent of the transistor? The transistor is a gm, a voltage control current source. The source is grounded, right, source is grounded, so we do not have to bother too much. On top, I have Rd, right. What is, what should I do with the other side of the Rd? Other side of the Rd should be grounded because again Vdd, right, so this grounds. From here, I go at the drain. What do I have? An infinite capacitor, an infinite capacitor, an infinite capacitor in an incremental sense is a, is a short circuit, right, so the capacitor is short, then what we end up with, we end up with RL here. Let me use a different color for Rd because that is how I have sketched it in the figure on the top, ok. So what will be the value of this gm, it will be gm times Vgs, right. In this case, hence it will be gm times Vg, ok, and from across which, which node am I interested in taking the output, clearly I am interested in taking the output across RL, right, so this is my V0, this is V0, ok. So if that is the case, what is the incremental V0? So note that in this case, RL and Rd are in parallel to each other, right, since RL and Rd are in parallel to each other, all the incremental current gm, gm Vg is flowing out of the parallel combination of Rd and RL and I am, by taking the voltage across RL, I am essentially taking the voltage across RL and Rd, parallel combination of RL and Rd for the purpose of this analysis, right. So V0 becomes equal to minus gm times Vg Rd parallel RL, ok. And if you bias your input side properly, this becomes minus gm times Vi times Rd parallel RL, ok, which means the incremental gain V0 over Vi becomes minus gm times Rd parallel, ok. So this is, so this is, clearly this is not as good as minus gm times RL, which we could have gotten if we had plugged RL in, instead of Rd, if we had the option of having access to both terminals of RL and I could have plugged RL in between the drain and the, and Vdd, but we could not do so and because, and what was the replacement? The replacement, the alternate architecture was to put Rd between Vdd and, between Vdd and the drain and RL is, is grounded, right. So and because, because now the current is getting shared, incremental current is getting shared between, note that this incremental current, this incremental current is getting shared between RL and Rd, right. Earlier all the incremental current was going into RL, because the incremental current is getting shared between RL and Rd, we are getting a lower gain, ok, ok. So one final thing let me ask you before we stop. Again we assumed C2 to be, we assumed C2 to be infinitely large. What do you think, I mean clearly you cannot again have an infinite capacitor, right. What do you think will be the value of C2 or what will be the constraint on the value of C2 when, if we have to choose a value so as to pass a, so as to pass a waveform of frequency omega naught, right. So essentially what I am asking is we, can you figure out what will be the constraint, what will be the, what will be the limit of C2 or what will be the constraint on C2, just like we figured out the constraint on C2 at the beginning of this, on this lecture, right. So I hope you can do it yourself, I will see you in the next lecture.