Lecture 12

[Music] welcome to this class and we are discussing rate matching module we discussed a part of it we took one example where in the code rate which was asked by the user was higher than the mother code rate which was generated by the ldpc encoder okay and we'll take another example wherein the code rate which is asked by the user now is lower than the rate 1x3 which is the mother code rate okay and we will see how this rate matching module Works in this case okay right so how rate matching can reduce the rate also that's the idea okay so we we saw how rate matching can increase the rate and that happens by dropping the bits at the transmitter okay we see how we'll see this now okay and we'll discuss another some of these modules if time permits in this class otherwise in the next class okay we'll discuss something called code block inter leaving and what is concatination and scrambling okay that will happen in the next class references are mentioned later in the slide right we'll discuss that okay so what we have seen until now is basically this again I'm recapturing this so that we understand where we are okay so transfer block comes here transfer block CRC is appended then the transfer block gets segmented okay then to and that segmented transform block is called code block to each code block code block CRC is appended then each of this segmented code block under goes ldpc coding okay output of that is at the rate 1x3 which is not the rate user has asked then this there is a block which is basically does the rate matching okay which matches the rate to the one matches rate 1x3 to the one which is asked by the user okay followed by modulation okay right we'll see that some other modules also come in between okay but this is what we have seen till now okay and the reverse process of that and we'll go through all of this in great detail but this is there to like make us understand how receiver actually works okay right so modulation opposite of modulation demodulation has to happen okay right then this rate matching module okay opposite of that okay there is something called rate recovery we'll see that in great detail but I'll just jump the gun and tell you what is this module doing okay so that this whole of this make this receiver chain makes sense okay now ldpc encoder works at the rate 1x3 so ldpc decoder is designed for that rate only okay so ldpc decoder also works at rate 1x3 but the rate what is coming here basically what is this is the rate which is asked by the user right because what is this rate this is let's say 6 you modulate it you demodulate it what will happen you'll get that rate back 62 when the ldpc decoder is designed to operate at rate 1x3 okay so what is this call so what will this module do it will take this 6 it'll map it back to 1x3 how is it done we'll see later okay right so you can see people some of the students say rate Dem matching but it's actually nicer name is rate recovery okay then you are recovering the rate okay which was asked by the user to one which is required by the decoder there's always one by three okay right this can be higher or lower but this is always 1 by 3 again the same idea that you don't want to design 20 odd ldpc decoder for each of the rate which is defined in the standard okay again the cost now okay so ldpc decoding there was Cal to four code blocks correct okay then each of them is getting decoded by the ldpc decoder then each of this code block has a CRC which gets validated okay and all these code blocks are put together they're concatenated and then this is basically what will you get you'll get a transfer block and at the end there will be this transfer block CRC gets validated pass on to a Mac layer done otherwise hybrid irq kicks in we we have discussed that but this is the outline of the receiver so this is now what we are going to see in this class is that this is rate 1x3 if the rate is lower here what needs to be done that's the idea okay right and you'll see that we'll take another user allocation okay resource allocation and work according to that okay because the reason is each of this MCS has its own rate okay whatever MCS 16 we took that's a predefined rate you cannot reduce the rate there okay so you have to move to another MCS index where the rate is lower than 1x3 correct okay and easiest possible example is mcs0 okay right that's the lowest possible rate and what is this code rate is 120 by 1024 it's 0.1 right lower than 3 correct so it satisfies our requirement of understanding how will a rate matching module work for this case okay but MCA 0 what is the modulation the four the modulation okay right and how many prb are allocated to this user I'm taking some number and prb equal to 10 fine okay it can be 50 it can be 275 also doesn't matter okay right so depending on this nprb okay the transport block size is going to change because you have more resources you'll send a Mac will send a larger size transfer block of course so this the transport block size is coupled to the number of prbs which is allocated to the user and the MCS which is allocated to the user okay once we see this formula which come much later you'll see all these parameters being used in calculating the transfer block size okay right now so the effective transport block size which is sent by the Mac in this case is only 368 bits look at we have come to the Other Extreme okay right how many prbs were there earlier 7 20 what was the MCS index 16 okay and the transfer block size was running into thousands of bits correct okay now it is only hundreds of bits and the reason is obvious this user is in a poor nnr condition and has a low data rate requirement fine so but what is going to happen now as soon as it is this transfer block comes to the physical layer 24bit tbcc is attached okay right total number of coded block we don't have to run the segmentation block here okay without running itself we know that how many segmented blocks will be there there'll be only one because it's much lesser than the number which is the 814 8 8448 okay that is the number okay much lesser than that of course like segmentation it'll go through the segmentation module but segmentation module will not segment it right so fine now the output of this the segmentation module what is this total number of coded block is 1 392 this needs to be encoded by the ldpc encoder correct and ldpc encoder can encode a certain selective sizes right which essentially means that encoder can only be of a particular length right if that length doesn't match if this length doesn't match what the ldpc encoder can encode what needs to be done there one needs to append the filler bits right okay so segmentation module is going to add that even though it's not going to segment it but it's going to append those filler bits so segmentation module has its role okay of appending the filler bits right okay so and why are we doing it because we want to understand how rate is done in this case but you have to go through this whole chain fine so you have to search for this minimum value of z c okay this is this table we did this exercise earlier also and what is this minimum value of z c that KB into z c should be equal to K right okay which is greater than equal to K Dash correct what is this what is K Das K Das is 392 okay K Das is transform Block Plus CRC without filler bits K is K Das plus filler bits right so what is happening here what is this number KB KB is 22 correct what is this number of systematic columns that is fixed remember that this is what we learned in the last class okay right do this math you have to search through this write a small module to do this exercise in the segmentation module okay so what is this 22 and you'll see that 18 is the zc is the lifting size which satisfies this condition okay what does coming out to be 396 what is this Z zc is the minimum number which makes sure that K is greater than equal to K Dash okay right so z c is 18 18 is somewhere sitting here okay so it gives us 396 how many filler bits need to be appended four okay 396 - 392 because ldpc encoder can encode only this size fine okay right so filler bits are add to match to the suitable lifting size and its number is four fine so what is happening here so total of one code block so what is the summary of this segmentation module here C is equal to 1 which is of size K which is 396 bits with filler bit f is equal to 4 correct okay and what will be the output in this case what will be the output length n is equal to 66 z c okay right ldpc and code output for each segmented block I written NR which is n okay what is this 66 into 118 okay 66 into 18 that is 118 now you see the rate exactly here also what will be the rate here rate will be K by n what is this 396 by 1188 exactly 1x3 okay mother code rate is always 1x3 fine ldpc and rate 396 by 118 which is 1x3 neatly done okay right fine but the code rate asked by the user is 0.1 that's the problem we are trying to understand and the design of rate matching module to handle that okay right so how do you do it now again we'll do the same exercise so how many bits which can be transmitted for this 10 prps that's the allocation which is done to this user how many bits you can transmit G total number you can transmit is G and what is e what is the difference between G and E let's recall e is G by C right e is basically the number of bits which you can transmit for each code block G is the number of bit which can which you are allowed to transmit for all the code blocks correct in this case e will be equal to G because C is 1 okay we'll see that but what is g 10 how many resources 10 prbs 162 where is this coming from let's recall okay how many one prb has how many resource elements 12 into 14 okay that is 168 - 6 for the pilots that's what it's coming from okay right so keep this in mind I can if the pilot increases or reduces we can do that okay then correspondingly this number will reduce okay because you're blocking certain extra sub carriers for the pilots right okay what is the modulation being used here here is four qu right so how many bits you can transmit 3 2 4 0 fine okay look at the difference now okay how many bits you have generated 188 how many you are allowed to transmit right 3 2 4 0 okay right and so length of the rate match code block e which I said is G by C so the total number of bits which you can transmit for this code blog is 32 40 because C is one okay right so before we go there what is happening here okay let's understand this rate is 1x3 rate asked by user is .1 that is 1 by 10 correct okay now for that rate what does that mean okay Rate One by 10 for each message bit you should generate nine more par bits but how many are generating only two right how will you how will you match this okay simple idea read those bits that's all okay that's what we are going to see okay right so that's where the circular prer will kick in and but before that we have to calculate those RV indices also for the hybrid AR that this k0 comes from that formula which I gave you in the last class okay right the same formula formula doesn't change and that's you'll get these four RV indexes okay because rate matching implements the hybrid arq also fine okay so what is happening here that's how the see what will the length of the circular buffer length of the circular buffer will will be n right how much is that n n is 118 correct okay so that you see this 11 188 and is a circular buffer and you let's say you transmitting rv0 how many bits you are allowed to transmit 3 2 4 0 right what will this rate matching module do so what it'll start reading from here 11 188 correct it you'll see that it is still not finished 32 4 go back and reread okay that's where the circular buffing is used okay but what the idea here is because you have generated lesser number of parity bits than what the user has asked for okay right then you basically reread those bits it's not the r transmitting you reread those bits and transmit them again the same coded block you transmit them again this is not hybrid RQ please keep in mind okay this is only rv0 okay and why are we running upon this condition is because you have generated higher code rate than what the user has asked for you have generated lesser number of P bits than what the user has asked for correct okay right where it is okay so we are actually done okay so for taking this example where in like we understand that that how do you generate a lower code rate from the higher code rate okay right again the idea is why is it done like that to reduce the implementation complexity fine how it actually done in the standard that's what I'm going to show you so we have what we have done till now is basically we have understood how rate matching module can increase or reduce the rate right so recall the bit output of ldpc encoder is decoded as D so this ldpc encoder is going to go into the rate matching module right so the bit input to the rate matching is there for these bits how many how many bits are going inside the rate matching module what is n correct okay that's what it is right and how many will be read out right and see the bit output of the rate match is denoted as e input is D output is e okay right and it makes sense to like when you coding it you know okay it is a b c d e f g h that's how the input outputs are okay it becomes very easy to remember that okay intentional okay right it's not given a fancy name it can be as simple as that right okay so how many bits you are reading out e for each code block okay so this is the input and output but I'll now I'll take you through how this rate matching module is actually defined in the standard the instructions given to implementing this rate matching module okay right so let's see that okay what is this that's how it is given I'm just like using exactly what is defined in the standard as I'm repeating myself the idea of this course is to make student read the standard understand how like how it is different from reading a book there are no intuitive insights in the standard okay the intuitive insights come by doing this kind of course wherein like somebody has already done it and they are able to tell books are also there but they come much later okay where like standard is defined so there are these people like you once do it then they know how to read it okay right so what is happening what are we denoting denoting this RV ID this is a redundancy version okay and it can go from 0 to three okay and so there's a rate matching output sequence how is it denoted EK that's how it is denoted so I'm reading the instruction I've just copied the instruction SE which are given in the standard okay is generated as follows so you have to from input is D how will you generate e which is the rate matched output from D that's what this in this instructions will tell you okay where K not is given by table 4. this table and I've shown you that table how this K not that RV is calculated right K K1 K2 K3 calculated right okay so So based on this you start reading from a particular RV ID okay 012 3 okay so what is happening you see this okay so before we get into this let me uh tell you one more thing okay that this what is the the job of rate matching module is also to remove these filler bits okay because filler bits are dummy bits they are not transmitted okay right and why were the filler bits added because we wanted ldpc encoder to work correct okay you see this so ldpc encoder has done its job it has taken in the encoder input with the filler bits okay it has encoded it okay right so and the this ldpc encoder is not going to change the position of these filler bits okay right it doesn't change that so where whatever was the position of the ldpc encoder bit the those bits are going to the position is going to remain same okay so you are going to reinsert those filler bits at the end of the ldpc encoder we understand what I'm saying here okay so what is happening here ldpc like I did not show it here okay so ldpc encoder there was this filler bits which were added and the output of this ldpc encoder there will be these filler bits whose position has not changed okay so you'll reinsert these filler bits okay right and they will be different from 0o and one you give them any number minus one okay right so what is happening here so J is index is a running index we okay so what is this while K is less than how many bits you are supposed to be reading k e bits okay e is K is an index for that right okay what happens so you see this if this you read what is this D what is d d is the input to the rate matching module correct okay what is K not K not is the RV index correct okay K not is given by according to the RV ID K not is a starting point okay so if k for the first RV what is the starting point K not is zero correct okay so what will happen here K not is zero because you're transmitting first RV ID J is what is J set two zero what is mod NCB that is the circular buffing NCB is what is equal to n in our case correct what will this index be d0 if d0 is not equal to null then you make that as the output that is the e0 because K is also set to zero okay let K is equal to Z see this that's the instruction k0 J is z okay right so and K 0 is also zero why is K 0 0 because there the first RV rv0 correct why is j0 because you set it to zero why is this mod NCB is a circular buffer okay right if this bit is not equal to null then you make that as output what will this output e0 right so you inre increase this what is the K becomes one right go back because this is this if because this while has not ended so what happens here then this is end if okay you come here J what becomes what is the value of J now J becomes one correct K has become one J has become one you'll see the use of this K and J okay I'll show you that immediately okay this V is not ended okay now what is happening here you see this come back here J what is the value of J one and what is the value of K that is also one so J is basically you read this come here J is the input index and K is the output index where is K being used to store into the output buffer J is being used to read from the input buffer fine so come here you look at this if J is one now K not is always zero because there RV Z so forget about that they always be set to zero okay now if D1 is let's say null okay just for example what'll happen then you come here you will not write that bit into the output buffer so K index doesn't get increase it's only the J index which is getting increase right okay that's how this dat matching is removing the null bits okay so the J input index has increased you get go to the next one because K is still K is only one as of now right you have read only one bit me you have written only one bit okay now what happens to the J index it becomes two if D2 is again null you again skip this come here okay J becomes three k is only one as of now because these two bits were null you have not recorded them in the output buffer correct okay if you don't hit the null bits then G and K will be same if you hit the null bits input index will be different from the output index because you have to skip those input bits okay what are those input bits those input bits which are written in the rate matching buffer correct okay what is this rate matching module doing okay look at this it is reading from the circular buffer and writing into some other buffer which is denoted as e correct that's what we saw that it reads from a larger size buffer right into a smaller buffer whose length is he do we understand this okay right that's how it is implemented okay and this is a circular buffering part so this is like one part of it another part of it I'll because I have to show you this there like there it's a little more sophisticated because it is if you read this this is like it continues I'll show you why this is there but we have not understood that part of the standard so I'll just skip it and show you what it has to calculate this e also right who's going to calculate the E rate matcher only okay so this is actually that for each of this module each of the coded block is going to calculate how many bits it can transmit basically the value of e right that's also needs to be done who is going to do that and that's what it is okay I'll skip all of this okay because we I have not taught you okay what is this telling you it is basically denote it has to calculate e okay denoting the ER the rate matching output sequence for the AR code block where the value of ER is determined as follows okay all these instructions they are only there to calculate the value of e okay and it has to take care of like myo it has to take care of certain other things also which I have not even taught you okay but if you so for each of this code block Ral to 0 to cus 1 okay right this needs to be calculated okay correct what's happening here then so look at this okay so if the what is this instruction telling you if this particular coded block is not scheduled okay transmitter has not scheduled this coded Block Set ER as zero because this code block is not allowed to be transmitted okay otherwise depending on certain conditions we are not I'm not going to talk about these condition because I'm not taught you okay what I'm going to show you here is okay if you ignore all this floor and seal here what is happening here NL qm they get cancelled if I just ignore the floor and the seal operation here okay this is flooring operation this is the seing operation here okay right what happens NL qm cancels NL qm what is the value of G you are getting G by C okay right that's this is only the E value calculation and why this what is this NL NL is the number of parallel myo layers you can transmit I'm not going to get into the detail of that because I not even taught you that okay right qm is a modation order okay so e this e calculation differs based on this the number of layers and the modulation order okay so that's what it is but for our study what is happening here is NL qm they cancel each other okay and E becomes G by C and that's what I have taught you number of bits which each module can each of this which are allowed to be transmitt for each of this coded block that is g by C fine so this is what it is analy the number of transmission layer that the transport block is mapped into NL for us it is NL is one okay right Q is the modulation order so whatever is the modulation order okay you put it over here gets canceled because this conditions come on based on this certain other requirement which I have not taught you right so as I said this is only e calculation that's what it is so G is a total number of coded bits available for transmission of the transmit of the transfer block G is what total number of bits e is G by C right okay and this is you can forget it because it was there in the standard I've left it for you okay if CB GTI is not present in the DC scheduling the transfer block and C Dash is the number of scheduled blocks I'm not going to talk about it because I'm not taught you what is DCI I not taught you CB GTA what is it I not taught you number of transmission layers okay but I had to tell you about rate matching module and that's a part of it okay right if you don't understand this if you simply fit in this e comes as G by C that's what is our requirement that's the key takeaway from this part of the standard okay what was required for us is this but e has also needs to be calculated okay so I'll stop here and then we'll continue in the next class so this is basically what we have learned in these two lectures is how rate matching is designed and what is the need of rate matching that's what we have learned okay thank you [Music] [Music] [Music]