Lec 19: Transistor sizing for asymmetric combinational circuits

[Music] [Music] so this is a lecture in the module 2 today we will be discussing the transistor sizing of asymmetric logic circuits so basically asymmetric inverters and inverter chains so we will first discuss logical effort of asymmetric Gates and why is it important in near threshold voltage regime and then we will discuss inverter chains there are several applications where nominal voltage or standard nominal voltage or super threshold voltage standard cells are used in near threshold or operated you using Supply voltages which can be called near threshold voltage or Sub sub threshold voltage so the same I same circuit is operated in several voltage domains for example in a mobile phone in the hibernate and active modes you would be operating the same circuit in different voltage domains so the standard cell library might have been sized for super threshold voltage regime because that is where you want high performance so you might have sized them according to those requirements and you might have kept balanced output R rise fall transition times for for a super threshold voltage operation so it doesn't mean that at near threshold voltage operation the same the standard C library would have balanced output transition times and the reason for that is that the current behaves differently bit terminal voltages in super threshold voltage regime the current behaves as a square law or a linear relationship with respect to Terminal voltages Gate to Source body to and drain to Source voltages whereas in super in the near threshold or sub threshold voltage regime the current behaves as a in exponentially it changes exponentially with gate to source and drain to source voltages for example in the standard Library used by the used in this paper they find that uh to balance the output transition times in super threshold voltage regime they have a ratio of p and ratio WN WP by WN of 2.7 whereas to balance the standard cell library to standard balance the output transition times in an inverter in near threshold voltage regime say the threshold voltage is4 volts they're operating at a vdd of volt itself suppose so in that case they are finding that the transition times are matched if WP by WN is8 so that's a huge difference so therefore when they use this standard cell library for near threshold voltage operation there would not be the output transition times would not be matched and output rise time would be quite small compared to Output fall time for a say a step input so the wp by WN would come out to be quite different but the but since all the standard cells are sized to have nearly same WP by WN Al so the r for output rise and output fall transition times though they would not be equal in near threshold voltage operation they would fall in a ratio so though they are not equal they would fall in a ratio and how do we deal with this situation we'll discuss as we go ahead as we go further now first let us calculate let us use back of the envelope calculations to calculate logical efforts of these Gates so let us first generalize say that the standard cell library is sized with WP by WN of s okay and you use a common standard s Library both in Stand sub superer threshold and near threshold voltage regime and the size is s s could be different from this 2.7 or from8 okay it could be an intermediate value so that it gives an it doesn't skew the output transition rise and fall transition times too much so in that case what is the effective so if you effective resistance of the transistor now if you this is a more quite a simplistic argument assigning a value of resistance to a transistor but that is an effective resistance and which one can obtain through simulations so so so this is an equivalent kind of resistance so you can obtain it from by extracting RC time constant suppose you you have an inverter you have a known capacitance CL and give a step input so you would have a rise at the output take out the rise time okay and had this been an RC network rst of P mfit keep the same CL here for this rise time if you give a step input if the voltage rises from Z to vdd as a step how much would be the rise time for this rise time to be there what is the value of R rst so rst for the same TR which you get from simulations so that is the rst value that you are fixing for the transistor rst of P likewise you get rst of N and then you will take a ratio and that ratio they are saying it turns out to be 2.7 okay rst of n they are calling rst here and now for this generalized standard cell library where WP by WN is s and they are all also applying a body bias to the N mosfit either a forward or a negative body bias so that the transition times are matched and uh for for suppose this s is smaller than two is larger than 2.7 then you'll have a output rise time which is smaller than output fall time then you can apply forward body BS to the body of the P mosit all the N mosit for all the N mosfets you can apply a body Bas and match the transition time so that's what they're doing here so the why so when they apply that body Bas the resistance of this equivalent resistance of the nmos fit changes to y * RSC so equivalent resistance of nmos pit changes to I'm sorry they're not applying body Bears to the pit they are applying an equal body bars to all the Enos devices because all the Enos devices are shared in a substrate in a planer technology so they are applying equal body bias to all the Enos fit transistors so that is easy from a layout point of view otherwise for pits you will have to bias each of the wells separately so when you apply body bias this goes from rst to y * rst for nominal voltage operation and Z * r s for near threshold voltage operation and what about the p mosit okay n mosit in nominal voltage n mosit would have an equivalent resistance P mosit when it's when WP by WN is equal to 2.7 would have resistance RS then they would have both equal resistances now when WP by WN is equal to S when WP by W is 1 then the equivalent resistance of P mosit by the same reasoning would be r s into 2.7 because the width of the pmosfet device has reduced by 2.7 times width of the pfet device has reduced by 2.57 times so it's so current is proportional to this is because current is proportional to width of the device so width of the device has reduced by 2.5 7 times and therefore the for the same terminal voltages the current would Reduce by 2.7 times it means resistance has equivalent resistance has increased by 2.7 times so for WP by WN is equal to S the equivalent resistance of p mosit is this into 2.7 by S by the same reason because current is now proportional to has increased by a value s so resistance has reduced by a value s for the same terminal voltages so that's why here this is the equivalent resistance is now 2.7 into RS divided by S likewise for SE near threshold or SE threshold voltage regime the wp by WN of8 balances the resistances then the resistance R and T near threshold are near threshold of both p moset and moset are equal now you have a size s means it will be8 rnt by S for the P fit okay so what is the value of logical effort now logical effort the authors are obtaining with respect to the standard template inverter for this it's as if what is the so how how is this logical effort now defined while the drive strength or switching current is equal the ratio of input capacitance of a gate to that of the reference inverter so this is how we can look at logical effort so what is The Logical effort of this inverter with respect to this inverter this is the standard template inverter so you're taking ratios of RC time constants switching RC time constants in this this the authors take that so this is equal to rc time constant of the so this is for output fall output fall okay so RC time constant how much would that be Y rst into the capacitance capacitance is C g into 1 + S because now you are assuming the gate capacitance of the p mosit and in un mosit per unit width to be equal divided by rst for the standard template inverter this one rst into the capacitance so capacitance would be if this inverter is driving similar inverter the capacitance scene would be 1 + 2.7 CG okay so now you cancel out the terms CG gone likewise s is also gone that's how you get Y into 1 + S / by 2 3.7 3.7 how about parastic delay so here they are assuming that for parasitic delay they are assuming that parasitic capacitance parasitic capacitance is equal to gate capacitance so what would be the parasitic capacit cap itance here it's equal to the gate capacitor means CP CP is therefore equal to 1.8 CG so what is the RC time constant so RC time constant for output discharge for the parasitic capacitance would be rst which is z * R st into equivalent the capacitance when you are driving a similar inverter which is 1 + S CG ided by rst for the inverter into 1 + 2.7 1 +8 I'm sorry 1 + 0.8 CG this is for the denominator is for this inverter and numerator is for this inverter so what does this turn out to be cancel out these terms then this turns out to be this value pfn likewise there likewise they have calculated other values of logical effort and that is Rise logical effort for output rise parasitic delay for output rise logical effort for output fall parasitic delay for output fall for example this is output rise paraset output rise RC time constant so you're driving a similar inverter so in that case it would come out to be 2.7 by s r s into 1 + S CG ided by S into 1 + 2.7 CG cancel out the terms so 2.7 into 1 + S divided 3.7 s that's what this turns out to be so similarly they calculate all these values now we use this in obtaining logical effort of a path and thereby of a logic path using these asymmetric Gates and using these for the delay optimization position now let us look at how do we use this to estimate the path delay for an inverter chain suppose this is driving a load capacitance C in let us call C in as x i X1 and cl L as XM M could be the number of stages so but m m could be odd or even this is I = 1 I = 2 I = 3 i = m -1 suppose the input is rising and you are dealing with near threshold voltage regime then for input Rising what is The Logical effort in near threshold voltage regime we know that g is as we had done earlier Z times because of the body by us so input is rising so output is falling so Z * 1 + S / 1.8 1.8 is for the standard template inverter the input capacitors so what is the delay of individual stage then it will be for input Rising it would be Z into 1 + S by 1.8 * suppose this is the first stage then it is X2 divided by X1 here the capacitance is X2 here it is X3 and here it is x m minus one so suppose you have odd number of if you have even number of stages then this m is odd for m is odd for even number of stages then you can write M as 2 I + 1 okay likewise for the so so now we have we have estimated here the rise time rise delay input rise delay of the first stage and the first stage is seeing a rise DeLay So here you'll have output sorry input rise delay output fall delay for this you'll have input fall delay so defa so what is that what is The Logical effort for fall for the inverter so output rise input fall output rise 0.8 / s into 1 + S divided by 1.8 into X3 by X2 okay so likewise you add all the terms and you get that for all the odd numbered inverters you will have input rise delay input rise DeLay So for all the odd numbered inverters you have this so you begin from 1 okay 2 i - 1 is 1 then 3 then five like that 2 I minus one so for all the odd numbered inverters you have this as the delay and for the all the even numbered inverters you have this as the delay okay so now so this is the total delay you have obtained now you use the method of logical effort that is you equate all the terms X2 I by X2 IUS 1 that is equate the path effort uh stage effort of all the stages and obtain the total DeLay So in this lecture we have discussed the back of the envelope calculation based in estimation of The Logical effort values for inverters using asymmetric gate sizing and also discussed inverter chain delays and how to optimize inverter chains using this modified method of logical effort for asymmetric gate sizes thank you [Music] a [Music]